1. Field of the Invention
This invention relates to a semiconductor storage cell for use in an electronic memory array and more particularly an improved dynamic storage cell adapted for integrated semiconductor circuit fabrication.
2. Description of the Prior Art
Semiconductor memory arrays incorporating semiconductor storage cells are in common usage for the purpose of storing digital information paricularly in conjunction with electronic data processing equipment. These storage cells have been classified in various ways depending on the particular structural features or mode operation. Thus, there have been developed memory cells having one device, two devices, three devices, four devices, six devices, and perhaps more. By "devices" is usually meant the number of transistors, either bipolar or field effect transistor in a given cell. An example of a one device field effect transistor memory is found in Dennard U.S. Pat. No. B 3,387,286. An example of a four device field effect transistor memory is found in De Simone et al. U.S. Pat. No. 3,836,892 and several of the references cited therein. Memories may also be classified in terms of whether they are DC stable (static) or AC stable (dynamic) the latter requiring regeneration.
Desirable aspects of a semiconductor memory array include high speed operation, dense packaging of a large number of cells on a single semiconductor substrate, and low power consumption. Further, each group of memory cells forming a memory array requires support circuits and a minimization of the number of support circuits desired is also an advantageous feature. In the case of a dynamic memory (AC stable) the retention time which determines how frequently the memory must be regenerated is also significant. Traditionally, the fastest memories have been the multi-device bipolar transistor memories with the corresponding disadvantage of occupying the greatest space and consuming the greatest amount of power. A slower memory such as a one device field effect transistor memory can be packaged much more densely and dissipates less heat. Another disadvantage of one device FET memory cells is a relatively low level output signal.